? 2003 fairchild semiconductor corporation ds011670 www.fairchildsemi.com april 1994 revised may 2003 74vhc273 octal d-type flip-flop 74vhc273 octal d-type flip-flop general description the vhc273 is an advanced high speed cmos octal d-type flip-flop fabricated with silicon gate cmos technol- ogy. it achieves the high speed operation similar to equiva- lent bipolar schottky ttl while maintaining the cmos low power dissipation. the register has a common buffered clock (cp) which is fully edge-triggered. the state of each d input, one setup time before the low-to-high clock transition, is trans- ferred to the corresponding flip-flop?s q output. the master reset (mr ) input will clear all flip-flops simultaneously. all outputs will be forced low independently of clock or data inputs by a low voltage level on the mr input. an input protection circuit insures that 0v to 7v can be applied to the inputs pins without regard to the supply volt- age. this device can be used to interface 5v to 3v systems and two supply systems such as battery backup. this cir- cuit prevents device destruction due to mismatched supply and input voltages. features high speed: f max = 165 mhz (typ) at v cc = 5v low power dissipation: i cc = 4 a (max) at t a = 25 c high noise immunity: v nih = v nil = 28% v cc (min) power down protection is provided on all inputs low noise: v olp = 0.9v (max) pin and function compatible with 74hc273 leadless dqfn package ordering code: surface mount packages are also available on tape and reel. specify by appending the suffix letter ? x ? to the ordering code. order number package number package description 74vhc273m m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74vhc273sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74vhc273bq (preliminary) mlp020b (preliminary) 20-terminal depopulated quad very-thin flat pack no leads (dqfn), jedec mo-241, 2.5 x 4.5mm 74vhc273mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74vhc273n n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
www.fairchildsemi.com 2 74vhc273 logic symbols ieee/iec pin descriptions function table h = high voltage level l = low voltage level x = immaterial = low-to-high transition connection diagrams pin assignments for pdip, soic, sop, and tssop pad assignments for dqfn (top through view) logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. pin names description d 0 ? d 7 data inputs mr master reset cp clock pulse input q 0 ? q 7 data outputs operating mode inputs outputs mr cp d n q n reset (clear) l x x l load '1' h hh load '0' h ll
3 www.fairchildsemi.com 74vhc273 absolute maximum ratings (note 1) recommended operating conditions (note 2) note 1: absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. the databook specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari- ables. fairchild does not recommend operation outside databook specifica- tions. note 2: unused inputs must be held high or low. they may not float. dc electrical characteristics noise characteristics note 3: parameter guaranteed by design. supply voltage (v cc ) ? 0.5v to + 7.0v dc input voltage (v in ) ? 0.5v to + 7.0v dc output voltage (v out ) ? 0.5v to v cc + 0.5v input diode current (i ik ) ? 20 ma output diode current (i ok ) 20 ma dc output current (i out ) 25 ma dc v cc /gnd current (i cc ) 75 ma storage temperature (t stg ) ? 65 c to + 150 c lead temperature (t l ) (soldering, 10 seconds) 260 c supply voltage (v cc )2.0v to + 5.5v input voltage (v in )0v to + 5.5v output voltage (v out )0v to v cc operating temperature (t opr ) ? 40 c to + 85 c input rise and fall time (t r , t f ) v cc = 3.3v 0.3v 0 ns/v 100 ns/v v cc = 5.0v 0.5v 0 ns/v 20 ns/v symbol parameter v cc t a = 25 ct a = ? 40 c to + 85 c units conditions (v) min typ max min max v ih high level input 2.0 1.50 1.50 v voltage 3.0 ? 5.5 0.7 v cc 0.7 v cc v il low level input 2.0 0.50 0.50 v voltage 3.0 ? 5.5 0.3 v cc 0.3 v cc v oh high level output 2.0 1.9 2.0 1.9 v v in = v ih i oh = ? 50 a voltage 3.0 2.9 3.0 2.9 or v il 4.5 4.4 4.5 4.4 3.0 2.58 2.48 v i oh = ? 4 ma 4.5 3.94 3.80 i oh = ? 8 ma v ol low level output 2.0 0.0 0.1 0.1 v v in = v ih i ol = 50 a voltage 3.0 0.0 0.1 0.1 or v il 4.5 0.0 0.1 0.1 3.0 0.36 0.44 v i ol = 4 ma 4.5 0.36 0.44 i ol = 8 ma i in input leakage current 0 ? 5.5 0.1 1.0 av in = 5.5v or gnd i cc quiescent supply current 5.5 4.0 40.0 av in = v cc or gnd symbol parameter v cc t a = 25 c units conditions (v) typ limits v olp quiet output maximum dynamic v ol 5.0 0.6 0.9 v c l = 50 pf (note 3) v olv quiet output minimum dynamic v ol 5.0 ? 0.6 ? 0.9 v c l = 50 pf (note 3) v ihd minimum high level dynamic input voltage 5.0 3.5 v c l = 50 pf (note 3) v ild maximum low level dynamic input voltage 5.0 1.5 v c l = 50 pf (note 3)
www.fairchildsemi.com 4 74vhc273 ac electrical characteristics note 4: parameter guaranteed by design t oslh = |t plh max ? t plh min|; t oshl = |t phl max ? t phl min|. note 5: c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained from the equation: i cc (opr.) = c pd * v cc * f in + i cc /8 (per f/f). the total c pd when n pieces of the flip-flop operates can be calculated by the equation: c pd (total) = 22 + 9n. ac operating requirements note 6: v cc is 3.3 0.3v or 5.0 0.5v symbol parameter v cc t a = 25 ct a = ? 40 c to + 85 c units conditions (v) min typ max min max f max maximum clock 3.3 0.3 75 120 65 mhz c l = 15 pf frequency 50 75 45 c l = 50 pf 5.0 0.5 120 165 100 mhz c l = 15 pf 80 110 70 c l = 50 pf t plh propagation delay 3.3 0.3 8.7 13.6 1.0 16.0 ns c l = 15 pf t phl time (ck - q) 11.2 17.1 1.0 19.5 c l = 50 pf 5.0 0.5 5.8 9.0 1.0 10.5 ns c l = 15 pf 7.3 11.0 1.0 12.5 c l = 50 pf t phl propagation delay 3.3 0.3 8.9 13.6 1.0 16.0 ns c l = 15 pf time (mr - q) 11.4 17.1 1.0 19.5 c l = 50 pf 5.0 0.5 5.2 8.5 1.0 10.0 ns c l = 15 pf 6.7 10.5 1.0 12.0 c l = 50 pf t oslh output to 3.3 0.3 1.5 1.5 ns (note 4) c l = 50 pf t oshl output skew 5.0 0.5 1.0 1.0 c l = 50 pf c in input capacitance 4.0 10.0 10.0 pf v cc = open c pd power dissipation 31 pf (note 5) capacitance symbol parameter v cc (v) (note 6) t a = 25 ct a = ? 40 c to + 85 c units typ guaranteed minimum t w (l) minimum pulse width (ck) 3.3 5.5 6.5 ns t w (h) 5.0 5.0 5.0 t w (l) minimum pulse width (mr ) 3.3 5.0 6.0 ns 5.0 5.0 5.0 t s minimum setup time 3.3 5.5 6.5 ns 5.0 4.5 4.5 t h minimum hold time 3.3 1.0 1.0 ns 5.0 1.0 1.0 t rec minimum removal time (mr ) 3.3 2.5 2.5 ns 5.0 2.0 2.0
5 www.fairchildsemi.com 74vhc273 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m20b
www.fairchildsemi.com 6 74vhc273 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
7 www.fairchildsemi.com 74vhc273 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-terminal depopulated quad very-thin flat pack no leads (dqfn), jedec mo-241, 2.5 x 4.5mm package number mlp020b (preliminary)
www.fairchildsemi.com 8 74vhc273 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20
9 www.fairchildsemi.com 74vhc273 octal d-type flip-flop physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n20a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
|
